1. Field of Invention
The present invention relates to a layout design of an electrostatic discharge (ESD) protection device. More particularly, the present invention relates to the layout design of an ESD protection device having metal runners that function as fuses for better electrostatic discharge protection.
2. Description of Related Art
Input signals to metal oxide semiconductor (MOS) integrated circuits (ICs) are supplied through the gate of a MOS transistor. If a high voltage is supplied to the gate terminal, the gate oxide layer may not be able to withstand the high voltage and soon breaks down. Although the operating voltage of an IC, which is around 5 V, will not cause voltage break down, voltages higher than the normal input voltage can sometimes be produced when the devices are transported by humans or machines. In fact, the sources for generating these abnormally high voltages are many. For example, electric charges can be produced through friction between surfaces or when the IC is unpacked from plastic packaging. The amount of static electricity generated this way can range from several hundreds volts to several thousand volts. If such high voltages are accidentally allowed to touch the pins of an IC package, voltage break down of the gate oxide layer of a transistor within the package is inescapable. Consequently, the transistor is unable to function properly leading to device failure.
To prevent damages to the MOS gate terminals, protective circuits are wired to all the pins of a MOS IC package. In general, protective circuits are also used in very large-scale integrated (VLSI) circuits. These protective circuits are normally installed between input/output (I/O) pads and the transistor gates in an integrated circuit. The protective circuits are designed such that they are capable of conducting or withstanding high voltages. Hence, these protective circuits provide an electrical path to a ground or a connection to an electrostatic discharge protective device on a power supply casing.
The mechanism for ESD protection is closely related to the snap-back mechanism between a drain terminal and a source terminal. When the snap-back mechanism of a protection device is triggered, the protection device will enter a low resistance state. Using a MOS transistor's protection device as an example, when an ESD event occurs, the protection device will be triggered. Subsequently, the voltage between the drain terminal and the source terminal will be lowered to a snap-back voltage, which is even lower than the triggering voltage. The snap-back voltage is used to absorb the ESD current and to protect the transistors that are used for carrying out logic operations in an integrated circuit.
In general, for VLSI circuits, large-sized MOS transistor structures are used as ESD protection devices. The zapping voltage of an ESD protection device must be restricted to a value below the so-called second break down voltage. The second break down voltage often occurs in the weak spots of a circuit, for example, local drain spots. The break down may be caused by some manufacturing defects. These defects tend to increase the production of hot channel current, and the heat generated by the current may lead to a second break down. Once a second break down occurs, large amounts of circuit currents will flow into these regions damaging the ESD protection device and causing it to malfunction.
In light of the foregoing, there is a need to provide a better design layout for the ESD protection device.